The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space [for C6413 device] and the Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
The McASP port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
Sound Normalizer 64 Serial 16
The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
A mechanistic understanding of core cognitive processes, such as working memory, is crucial to addressing psychiatric symptoms in brain disorders. We propose a combined psychophysical and biophysical account of two symptomatologically related diseases, both linked to hypofunctional NMDARs: schizophrenia and autoimmune anti-NMDAR encephalitis. We first quantified shared working memory alterations in a delayed-response task. In both patient groups, we report a markedly reduced influence of previous stimuli on working memory contents, despite preserved memory precision. We then simulated this finding with NMDAR-dependent synaptic alterations in a microcircuit model of prefrontal cortex. Changes in cortical excitation destabilized within-trial memory maintenance and could not account for disrupted serial dependence in working memory. Rather, a quantitative fit between data and simulations supports alterations of an NMDAR-dependent memory mechanism operating on longer timescales, such as short-term potentiation.
We assessed memory alterations in a visuospatial delayed-response task (Fig. 1a) on two coexisting temporal scales: single-trial working memory precision as a proxy of active memory maintenance during short delays, and serial dependence of responses on previously memorized stimuli16,17 (serial biases, Fig. 1b) as a read-out of passive information maintenance across trials. Our results show reduced serial dependence but intact working memory precision in both patient populations. Neural correlates of this task have been identified in monkey prefrontal cortex18,19,20, inspiring computational models that can capture key aspects of neural dynamics and behavior18,21,22. The biophysical detail of these models permits to investigate how NMDAR hypofunction at different synaptic sites affects circuit dynamics and working memory. Candidate mechanisms are a disturbed balance between cortical excitation and inhibition (excitation/inhibition balance), as it is observed in schizophrenia and in studies using NMDAR antagonists (e.g., ketamine)2,6,23,24, and alterations in NMDAR-regulated short-term synaptic potentiation3,4,5,25. In the modeling section of this study, we systematically test the potential of these candidate mechanisms for explaining our behavioral findings. We conclude that a reduction in short-term potentiation in a network model of working memory most parsimoniously reproduces the experimentally observed memory alterations in schizophrenia and anti-NMDAR encephalitis.
In this study, we assessed working memory alterations in two patient groups linked to NMDAR hypofunction, and hypothesized that their shared clinical and neurobiological features should be reflected in qualitatively similar behavioral patterns. In accordance with this reasoning, we found a drastic reduction of working memory serial dependence both in patients with anti-NMDAR encephalitis and schizophrenia, as compared to healthy controls. In contrast, we did not find memory maintenance deficits on timescales of a few seconds, suggesting that cognitive deficits in these patients8,12 might be partly explained by the disruption of long-lasting, inactive memory traces, and a lacking integration of past and current memories. Our modeling results show that simple alterations in cortical excitation (hypotheses II and III), as proposed by current theories of NMDAR hypofunction in schizophrenia6,24,27, cannot fully explain these behavioral findings. Instead, altered serial dependence is mechanistically accounted for by a disruption in slower dynamics, here specified as NMDAR-dependent associative STP (hypothesis I) that is triggered by sustained delay activity and influences memory representations in upcoming trials. Our results suggest that clinical reports of short-term memory alterations in schizophrenia and anti-NMDAR encephalitis could be understood in the light of reduced synaptic potentiation25. This is consistent with in vitro studies, which have demonstrated the dependence of STP on specific subunit components of the NMDAR3,4, and reduced STP in genetic mouse models of schizophrenia35. Importantly, our modeling is not incompatible with altered cortical excitatory or inhibitory tone as a result of hypofunctional NMDARs. Rather, it states the necessity of assuming alterations in a mechanism operating on longer timescales, such as STP. For instance, diminished STP alongside symmetric effects on both E-E and E-I synapses could maintain the excitation/inhibition balance and thus stable delay activity, while interrupting passive between-trial information maintenance.
Future studies should address the effects of pharmacological NMDAR blockade on serial dependence. These studies could unequivocally confirm the role of the NMDAR for trial-history effects in working memory, and at the same time allow to ask more specific questions: On the one hand, serial dependence effects under different NMDAR antagonists should vary according to how blocking specific NMDAR subunits modulates synaptic potentiation at different timescales3. Our results cannot address subunit specificity because anti-NMDAR encephalitis (and possibly schizophrenia9) is associated with hypofunction of the GluN1 subunit, which is contained in all NMDARs36,37. On the other hand, pharmacological studies in combination with neural recordings could reveal how trial-history representations are affected by the blockade of NMDARs18,38. In rodents, long-term pharmacological experiments during behavior could be complemented with in vitro studies to assess STP directly. Finally, pharmacological studies would clarify if the alterations in serial dependence occur as a result of acute NMDAR hypofunction or whether they depend on compensatory changes in STP that arise after early, acute phases of cortical excitation/inhibition imbalance in these diseases (e.g., as a long-term adjustment of the probability of presynaptic neurotransmitter release).
Interestingly, a reduction in serial dependence has recently been reported for patients with autism51, a disease also associated with NMDAR hypofunction52 and alterations in synaptic potentiation25. Further, as for autism, our findings of reduced serial dependence are compatible with normative accounts of information processing in schizophrenia. Classic theories and recent studies have reported an underweighting of past context, or in Bayesian terms, learned priors, and an overweighting of incoming perceptual information in patients with schizophrenia42,53,54 and NMDAR hypofunction55. Long-lived traces of past stimuli could serve as Bayesian priors to perception and memory, and a disruption of STP might be regarded as a biological implementation of a reduced usage of priors in schizophrenia and anti-NMDAR encephalitis. 2ff7e9595c
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